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VHDL DESIGN REFERENCE TABLE

Statement

Template

 

Example


LIBRARY

USE

LIBRARY library_name;
USE volume_name.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY

PORT

ENTITY entity_name IS
      PORT(
                port declarations);
END entity_name;

ENTITY control_chip IS
      PORT( in_sig : IN STD_LOGIC;
                 out_sig : OUT STD_LOGIC);
END control_chip;

ARCHITECTURE

ARCHITECTURE arch_name OF entity_name IS
      signal declarations
BEGIN
      concurrent statements
END arch_name;

ARCHITECTURE a0 OF control_chip IS
      SIGNAL out_net : STD_LOCIC;
      out_sig <= out_net;
BEGIN
      exchange : PROCESS (clk);
      BEGIN
           IF (clk = 1) THEN
                out_net <= in_sig;
           END IF;
      END;
END control_chip;

TYPE

TYPE collective_name IS (individual_names .....);

TYPE mode IS (fast, medium, slow);

PROCESS

process_name:PROCESS (sensitivity_list)
BEGIN
           sequential statements
END process_name;

exchange : PROCESS (clk)
BEGIN
      IF (clk = 1) THEN
           out_net <= in_sig;
      END IF;
END exchange;
 

CASE

CASE multi_value_statement IS
      WHEN first_value =>
                sequential statements
      WHEN second_value =>
                sequential statements
      ............. etc.
END CASE;
 

CASE count IS
      WHEN 0 =>
                out_net <= 0;
      WHEN 1 =>
                out_net <= in_sig;
      WHEN others =>
                out_net <= Z;
END CASE;

FOR

FOR variable IN range LOOP
           sequential statements
END LOOP;

FOR i IN 0 to 8 LOOP
           x_ram(i) <= in_sig AND in_bus(i);
END LOOP;

IF

 
ELSIF
ELSE

IF boolean_statement THEN
           sequential statements
ELSIF boolean_statement THEN
           sequential_statements
ELSE
           sequential_statements
END IF;

IF (prioity_sig_one = 1) THEN
           service_procedure (1);
           out_net <= 1;
ELSIF (prioity_sig_two = 1);
           service_procedure (2);
           out_net <= 1;
ELSE out_net <= 0;
END IF

WAIT

WAIT ON sensitivity_list;
WAIT FOR time_period;
WAIT UNTIL boolean_expression_true;

WAIT ON clk, reset;
WAIT FOR 100 ns;
WAIT UNTIL (in_sig = 1);

EXIT

EXIT;

EXIT;

 

EXIT WHEN boolean_expression_true;

EXIT WHEN (in_sig = 1);

TYPE       RECORD

 

TYPE record_name IS RECORD
           signal declarations
END RECORD;

TYPE two_entry_record IS RECORD;
      entry_one : STD_LOGIC_VECTOR(0 TO 4);
      entry_two : STD_LOGIC_VECTOR(0 TO 8);
END RECORD;

TYPE       ARRAY

TYPE array_name IS ARRAY(range) OF record;

TYPE table IS ARRAY(0 TO 46) OF two_entry_record;



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(c) Compiled by B V Wood.

 


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