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VHDL DESIGN TECHNIQUES


These code fragments showing useful techniques. They show just enough information to illustrate a technique and as a quick reminder for the future. The first three examples show how arithmetic operations can be performed using conversion statements and unsigned data types.

  • Convert STD_LOGIC_VECTOR to INTEGER.

    • Data defined as: address     : in STD_LOGIC_VECTOR(8 DOWNTO 0);
    Solution: VARIABLE address_int     : INTEGER 0 to 255;
    address_int     := CONV_INTEGER(UNSIGNED(address));
    Application: array(address_int)   := data; -- example of addressing an array.

  • Increment a count giving a STD_LOGIC_VECTOR result.

    • Data defined as: data_out             : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
    VARIABLE cnt   : INTEGER; -- internal count.
    Solution: cnt               := cnt + 1; -- e.g. incremented every clock pulse.
    data_out   <= CONV_STD_LOGIC_VECTOR(cnt,24);

  • Increment a count with STD_LOGIC_VECTOR input and output.

    • I/O Data as: data_in     : IN STD_LOGIC_VECTOR(23 downto 0);
    data_out   : OUT STD_LOGIC_VECTOR(23 downto 0);
    Solution: SIGNAL d;           : UNSIGNED (23 DOWNTO 0);         -- internal signals
    SIGNAL q;           : UNSIGNED (23 DOWNTO 0);         -- for data type conversions.
    CONSTANT one : UNSIGNED(23 downto 0)   := ( 0=>'1', others=>'0'); -- define 000001h.
    (in process:) d                <= UNSIGNED(data_in);       -- internal data type conversion.
    data_out   <= STD_LOGIC_VECTOR(q);
    q                <= d + one;                             -- arithmetic operation.

  • Set operations to occur at set (absolute) times.

    • In the architecture section set:- SIGNAL time2accum_ram_a   : BOOLEAN   := FALSE;
    In the main section set:- time2accum_ram_a   <= FALSE,   TRUE AFTER 56.5 us;
    In a process use:- WAIT UNTIL time2accum_ram_a   = TRUE;


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    (c) Compiled by B V Wood.

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