-- state_mc.vhd   State machine  template example.

LIBRARY ieee; USE ieee.std_logic_1164.all ;

ENTITY state_machine IS
  PORT(
     clock            : IN    STD_LOGIC;                     
     reset            : IN    STD_LOGIC;  
     event_one        : IN    STD_LOGIC; 
     event_two        : IN    STD_LOGIC;
      :
     etc. 
                        
     action_one       : OUT   STD_LOGIC;   
     action_two       : OUT   STD_LOGIC;
      :  
     etc.             : OUT   STD_LOGIC);                    
END state_machine;                          

ARCHITECTURE example OF state_machine IS

     TYPE state IS (idle, first, second, .... etc.);
     SIGNAL present_state, next_state : state;
     SIGNAL action_one_net, action_two_net, ..... etc. : STD_LOGIC;

BEGIN
     action_one   <= action_one_net;
     action_two   <= action_two_net;
      :
     etc.

     update : PROCESS (reset, clock)
     BEGIN
   	     IF (reset = '1') THEN 
	 present_state <= idle;
	     ELSIF (clock'EVENT AND clock='1') THEN
	 present_state <= next_state;
	     END IF;
    END PROCESS update;

    sequencer : PROCESS (present_state, event_one, event_two,... etc.)
    BEGIN
      	 CASE present_state IS

             WHEN idle =>                                          
 	     	action_one_net  <=  ....... ;
 	    	action_two_net  <=  ....... ;
            	 :
              	etc.

    		IF (event_one = '1') THEN
			next_state <= first;
		ELSIF (event_two = '1'; THEN
			next_state <= .....;
		ELSIF .......
		  ........;	
		  etc.

		END IF;

            WHEN first =>                                          
 	        action_one_net   <= .... ;
 	        action_two_net   <= .... ;
                 :
                etc.

 		IF (event_.... = '1') THEN
			next_state <= ..... ;
		ELSIF ...... etc. 
		END IF;
				                  
                next_state <= .... ;

            WHEN second =>
                  ..... etc.
 
	END CASE;

    END PROCESS sequencer;
END example;